Design of a 20MHz 1.5mW 4-bit Flash ADC
An implementation of a 4-bit Flash ADC architecture with a sampling frequency of 20MHz, maximum power draw of 1.5mW.
This post is licensed under CC BY 4.0 by the author.
An implementation of a 4-bit Flash ADC architecture with a sampling frequency of 20MHz, maximum power draw of 1.5mW.